1. Field
Embodiments of the invention relate to the field of image sensors, and more particularly to multiple slope column parallel analog-to-digital conversion for image sensors.
2. Background Information
Image sensors are ubiquitous. They are widely used in digital still cameras, digital video cameras, cellular phones, security cameras, medical devices, automobiles, and other applications.
Many image sensor applications benefit from fast processing speed. One way to achieve a fast processing speed is to increase the speed with which the image sensor is able to read out a captured image. The readout circuitry of image sensors commonly includes analog-to-digital (A/D) converters that convert analog voltages output from the pixel array into digital values used to construct a digital image. Column parallel A/D conversion architectures, where each column readout line or bit line is electrically coupled to a corresponding A/D converter, have been used to increase the readout speed of image sensors.
One type of readout uses a single-ramp single-slope (SRSS) column parallel A/D conversion. The term single ramp means that the reference voltage ramp signal makes only a single pass over the full reference voltage ramp range. The term single slope means that the reference voltage ramp signal has a single constant slope across the full reference voltage ramp range.
FIG. 1 is a block diagram of image sensor 100 having a column parallel A/D conversion architecture. The image sensor includes control circuitry 102, pixel array 104, readout circuitry 120 and digital processing logic 128. For simplicity of illustration, the illustrated pixel array includes only first column 106-1 having four pixel cells 108, and second column 106-2 having four pixel cells 108. It is to be appreciated that actual image sensors commonly include from hundreds to thousands of columns, and each column commonly includes from hundreds to thousands of pixels.
During use, after each pixel cell has acquired its image data or charge, the image data or charge may be read out of the pixel cells to readout circuitry 120 on column readout lines or bit lines 110-1, 110-2. There may be one bit line per column of the pixel array, and one row of pixel cells may be read out at a time using the bit lines for all of the columns. The readout circuitry may include a separate A/D converter 114-1, 114-2 for each corresponding bit line and/or column of the pixel array. That is, each column may share a portion of the readout circuitry that includes a corresponding A/D converter 114. As shown, each bit line and/or column may also have a corresponding column amplifier 112-1, 112-2 to amplify the image data or charge.
Each A/D converter includes corresponding comparator 116-1, 116-2 and latch 118-1, 118-2. Each of the comparators has two input terminals. The amplified image data from the column amplifiers may be provided to non-inverting input terminals of the comparators (i.e., the “+” terminals in the illustration). The readout circuitry also includes voltage ramp generator 122. The voltage ramp generator may generate and output a voltage ramp signal (VRAMP). The voltage ramp signal may be coupled with inverting input terminals of the comparators (i.e., the “−” terminals in the illustration). The voltage ramp signal may ramp up, for example in a saw tooth voltage ramp, from an initial voltage (e.g., 0V) to a final, full scale voltage (VFS). In another implementation, the + and − terminals may be exchanged. In some implementation, a single-ended comparator may be used, which takes a single input that is equal to the difference between VRAMP and a column amp output.
The readout circuitry also includes a counter 124. The counter increments while the voltage ramp signal (VRAMP) is applied. By way of example, the counter may be an N-bit counter, where N represents the resolution in bits of the A/D converters and/or the number of bits in the digital output values. Commonly, N may range from about 6-bits to 12-bits, or more. During each A/D conversion, the N-bit counter may increment from 0 to 2N−1. By way of example, in the particular case of 8-bits, the counter may count from 0 to 255, where each different count may represent a different digital level to which analog voltages from the pixel cells are to be mapped during A/D conversion. The counter may increment during clock cycles such that an N-bit A/D conversion may take approximately 2N clock cycles to complete. The counter is coupled to provide output counter signal 126 to each latch 118-1, 118-2 for each corresponding column.
The comparators may compare the input voltage ramp signal (VRAMP) with the input amplified analog input voltages from the pixel cells (e.g., of the row being output). The outputs of the comparators are coupled to the inputs of the corresponding latches. When a comparator determines that the input voltage ramp signal (VRAMP) matches the amplified analog input voltages from the corresponding pixel cell in the corresponding column, the corresponding latch may latch output counter signal 126. The latched counter signal may represent the digital level to which the amplified analog input voltage from the pixel cell has been mapped during the A/D conversion. When the voltage ramp signal does not match the amplified analog input voltages from the corresponding pixel cell in the corresponding column, then the corresponding latch does not latch the output counter signal (e.g., VRAMP is allowed to further increase while the counter continues to count until at some point the values match). In an alternate implementation, rather than a global counter and local latches, local counters may be used, and when a comparator triggers, the corresponding local counter may stops counting. The latched counter signal values may be output from the latches to digital processing logic 128. If desired, the values may be transferred in parallel to a buffer (e.g., a random access memory buffer), and then sequentially output to the digital processing logic.
Such an SRSS A/D conversion is commonly used to readout image data of image sensors. However, the use of such SRSS A/D conversions generally tends to provide relatively slow conversion times (e.g., of 2N clock cycles). In various applications, such slow conversion times tend to have drawbacks, especially when relatively high resolutions are used. Reducing the conversion time would offer certain advantages.